基于FPGA的卷积神经网络加速模块设计

梅志伟,王维东

Design of Convolutional Neural Network acceleration module based on FPGA

Zhiwei Mei,Weidong Wang

表4 VGG?16卷积层加速性能

Table 4 The acceleration performance of convolutional layers of VGG?16

VGG?16网络层 乘加数量 时间(ms) 性能(GOPS) 乘加阵列效率 conv1 0.0867 G 9.06 19.27 9.35% conv2 1.8496 G 18.16 203.71 99.51% conv3 0.9248 G 9.05 204.39 99.80% conv4 1.8497 G 18.18 203.49 99.40% conv5 0.9248 G 9.06 204.16 99.73% conv6 1.8497 G 18.38 201.27 98.32% conv7 1.8496 G 18.18 203.49 99.40% conv8 0.9248 G 9.29 199.11 97.28% conv9 1.8496 G 18.58 199.11 97.27% conv10 1.8496 G 18.58 199.11 97.27% conv11 0.4624 G 5.32 173.84 85.03% conv12 0.4624 G 5.32 173.84 85.03% conv13 0.4624 G 5.32 173.84 85.03% 卷积层 15.347 G 162.48 189.03