基于FPGA的卷积神经网络加速模块设计

梅志伟,王维东

Design of Convolutional Neural Network acceleration module based on FPGA

Zhiwei Mei,Weidong Wang

表2 AlexNet硬件加速性能

Table 2 The hardware acceleration performance of AlexNet

AlexNet层数 卷积核/步长 时间(ms) 乘加阵列效率 conv1 11×11/4 11.3 9.10% conv2 5×5/1 4.4 98.42% conv3 3×3/1 1.7 81.84% conv4 3×3/1 2.6 83.66% conv5 3×3/1 1.8 81.66% fc1 6×6/1 12.1 3.07% fc2 1×1/1 5.5 3.00% fc3 1×1/1 1.4 2.74%