Error floor of Low-density Parity-check (LDPC) codes, which is the performance of LDPC codes on high SNR area, still attracts a lot of attention now. It is of great concern for potential applications of LDPC codes to data storage applications, which require the code to maintain the near capacity error correcting performance down to frame error rates 10-12. Software simulation is normally applied to evaluate their error correcting performance. With a high-end PC, the bit error rate (BER) of 10-7 can be reached within about 10 hours. However, to get to lower error rate level, the time consuming will be intolerable. In concern with this situation, hardware acceleration system can be developed to make the evaluation much faster. This paper presents an FPGA platform implementation for LDPC code evaluation to investigate the error floor performance. The hardware evaluation platform features by fast speed and high precision. A throughput of 120Mbps is achieved and the BER curve can reach beyond 10-11 within one hour. This emulation speed is over ten thousand times higher than that of software simulation. With this high throughput, the efficiency of simulation to investigate the error floor performance can be highly increased. Additionally, based on this design, simulation of any LDPC codes with shifting or quaci-cyclic feature can be implemented similarly. Some modification will be needed in encoding and decoding modules. The construction of the platform is presented and the modules within the platform such as LDPC encoder, decoder, random number generator, FIFO, and AWGN noise generator are described in this paper. The PCI software interface and FPGA implementation result are also presented. The implementation results show that the design is very efficient in compare with some popular competitors
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